With the development of high-throughput sequencing technology， massive genome sequence data provide a data basis to understand the structure of genome. As an essential part of genomics research， splice site identification plays a vital role in gene discovery and determination of gene structure， and is of great importance for understanding the expression of gene traits. To address the problem that existing models cannot extract high-dimensional features of DNA （DeoxyriboNucleic Acid） sequences sufficiently， a splice site prediction model consisted of BERT （Bidirectional Encoder Representations from Transformers） and parallel Convolutional Neural Network （CNN） was constructed， namely BERT-splice. Firstly， the DNA language model was trained by BERT pre-training method to extract the contextual dynamic association features of DNA sequences and map DNA sequence features with a high-dimensional matrix. Then， the DNA language model was used to map the human reference genome sequence hg19 data into a high-dimensional matrix， and the result was adopted as input of parallel CNN classifier for retraining. Finally， a splice site prediction model was constructed on the basis of the above. Experimental results show that the prediction accuracy of BERT-splice model is 96.55% on the donor set of DNA splice sites and 95.80% on the acceptor set， which improved by 1.55% and 1.72% respectively， compared to that of the BERT and Recurrent Convolutional Neural Network （RCNN） constructed prediction model BERT-RCNN. Meanwhile， the average False Positive Rate （FPR） of donor/acceptor splice sites tested on five complete human gene sequences is 4.74%. The above verifies that the effectiveness of BERT-splice model for gene splice site prediction.

To improve the performance of gait recognition based on smartphone accelerometer, a recognition method based on Multiple Classifier Fusion (MCF) was proposed. Firstly, as the gait features extracted from the existing methods were relatively simple, the speed variation of the relative gradual acceleration extracted from each single gait cycle and the acceleration variation per unit time were taken as two new types of features (16 in total). Secondly, combing the new features with the frequently-used time domain and frequency domain features to form a new feature set, which could be used to train multiple classifiers with excellent recognition effect and short training time. Finally, Multiple Scale Voting (MSV) was used to fuse the output of the multiple classifiers to obtain the final classification result. To test the performance of the proposed method, the gait data of 32 volunteers were collected. Experimental results show that the recognition rate of new features for a single classifier is increased by 5.95% on average, and the final recognition rate of MSV fusion algorithm is 97.78%.

In the hybrid wired/wireless network, the traditional Transmission Control Protocol (TCP) versions in wired network simply ascribe packet loss to congestion, which causes unnecessary performance degradation. To solve this problem, a new adaptive control algorithm based on fuzzy theory was proposed. It selected new network status parameters, and used fuzzy loss differentiating method to make comprehensive evaluation out of network status, and it was based on feedback theory method, finally built an adaptive control model, i.e. getting the evaluation result set, then yielding the Transmission Performance Index (TPI) by summing up the result sets weighting elements, which entered into next evaluation cycle as one of the input factors and also adjusted the factors weights. The simulation results show this algorithm better reflects the real congestion status of hybrid network, has better network adaptability and performs better than current main TCP mechanisms. This algorithm, on the background of multi-parameters and using fuzzy methods, makes new explorations of hybrid network congestion and its adaptive control research.

It is a widely accepted approach to use wide data bus to increase the data accessing speed. However, this method causes the inconvenience on reading and writing data in bytes. The common operation mechanism of current mainstream SDRAM memory chip was analyzed, and a new byte alignment method was proposed for the SDRAM controller. Based on the given byte-address and input data, the new method could generate correct address and byte control signals, also aligned the bytes to the corresponding positions. The architecture and processing flow were illustrated in detail, as well as the implementation on Field Programmable Gate Array (FPGA) chips. Compared with other schemes based on memory cache and twice-memory-access, this method costs fewer hardware resources and memory bandwidth.